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NOT RECOMMENDED FOR NEW DESIGNS
Application Information
Protection from ESD
It is a fact that ESD is the primary cause of failure in electronic systems. Transient Voltage Suppressors(TVS) are an ideal choice for using as
ESD protection devices. They have the capability to clamp the incoming transient to such a low level that the damage to the circuit beyond the
device is prevented. Surface mount TVS are the best choice for minimum lead inductance. DLP3V3DTZ is designed to be used as two
unidirectional or single bidirectional protection device in a circuit. They serve as parallel protection elements, connected between the signal line to
ground. It will present a high impedance to the protected line up to 3.3 volts. As the transient rises above the operating voltage which is the
breakdown voltage of the device, the TVS diode becomes a low impedance path diverting the transient current to ground.
Dynamic Resistance to Calculate Clamping Voltage
At times PCB designers need to calculate the clamping voltage V CL . For this reason the dynamic resistance in addition to the typical parameters is
listed here. The voltage across the protected circuitry can be calculated as following:
V CL = V BR + Rd * Ipp (also V CL = Vz + Rd*Ipp....for accuracy)
e.g. If Ipp = 1A, V CL = Vz + Rd*Ipp = 5.6 V (from fig. 9) + 1A*0.115 Ohm = (5.6+0.115)V = 5.715 V (close to actual measured Value)
Where Ipp is the peak current through the TVS Diode. The short duration of the ESD has led us to a widely adapted classical test wave, 8/20 μ S
and 10/1000 μ S surges. Since Zzt remains stable for a surge duration less than 20 μ S, the 2.5 μ S rectangular surge is sufficient for use.
Peak Pulse Power Calculation
The following relation fits well for pulse width less than 10 mS.
Ppp = K (td)
-0.5
e.g. Ppp = 372 watts for pulse width(td) of 20 μ S, then 372 watts = K (20)
and K = 372/(20)
-0.5
-0.5
= 372* √ 20 = 1663.63
Now, Ppp when td = 50 μ S: Ppp =1663.63 (50)
= 1663.63/(50)
-0.5
0.5
= 1663.63/( √ 50) = 235.27 watts (close to measured value see fig. 2)
Tips for Circuit Board Layout
Correct layout of the circuit board plays a critical role in preventing ESD induced failures. Some of useful guidelines are given below:
- Trace length between the TVS diode and the circuit or line to be protected should be kept to a minimum.
- Always place a TVS diode as close as possible to the input terminals or connectors if one is required.
- Try to avoid or minimize power and ground loops or any other conductive loops.
- Try to use ground planes whenever feasible rather than a simple ground trace.
- The path to ground for the ESD transient return should be as short as possible.
Ordering Information (Note 4 & 6)
Device
DLP3V3DTZ-7
Packaging
SOT-23
Shipping
3000/Tape & Reel
Notes:
6. For packaging details, go to our website at http://www.diodes.com/datasheets/ap02007.pdf.
Marking Information
A07 = Product Type Marking Code
A07
YM = Date Code Marking
Y = Year (e.g., T = 2006)
M = Month (e.g., 1 = Janurary)
Date Code Key
Year
Code
2006
T
2007
U
2008
V
2009
W
2010
X
2011
Y
2012
Z
Month
Code
Jan
1
Feb
2
Mar
3
Apr
4
May
5
Jun
6
Jul
7
Aug
8
Sep
9
Oct
O
Nov
N
Dec
D
DS30669 Rev. 3 - 3
6 of 8
DLP3V3DTZ
? Diodes Incorporated
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